1. Field of the Invention
The invention concerns a process for intermediate amplification of digital signals, with amplitude and pulse regeneration, wherein the pulse regeneration comprises the following process steps: derivation of a receiving pulse signal from a received signal, reading the bits of the signal received with the receiving pulse signal into a buffer memory and reading out the bits with a local transmission pulse signal. The invention further concerns an intermediate amplifier for digital signals, with an amplitude and a pulse regeneration circuit. The pulse regeneration circuit includes a receiving pulse signal derivation circuit, a buffer memory, a control circuit and a local transmission pulse signal generator. A T7200 Multi Port Repeater Unit Controller of the AT&T company as described in its data sheet is an intermediate amplifier. The T7200 intermediate amplifier is intended for CSMA/CD (Carrier Sense Multiple Access/Collision Detection) access process according to the IEEE Standard 802.3 and satisfies the requirements relative to this process and standard. The CSMA/CD process is used in particular in connnection with computer networks.
2. Description of the Related Technology
FIG. 1 shows the fundamental configuration of a CSMA/CD computer network schematically. Computers T.sub.1 are connected with each other by transmission channels, so-called K.sub.1 segments. An intermediate amplifier R.sub.1 also referred to as a repeater, is located between each of the individual segments. The repeater regenerates the digital signals transmitted through the transmission channels K.sub.1 relative to both their amplitude and their transmission pulse. The amplitude regeneration is necessary as the digital data signals are weakened during their transmission in the transmission channels.
It will become apparent in the following from FIG. 2, why pulse regeneration is required. FIG. 2a reproduces the transmitter pulse signal, while FIG. 2b shows the transmitter data signal at the inlet of a transmission channel K.sub.1. At the inlet of a transmission signal K.sub.1 and at the outlet of a repeater R.sub.1, the transmitter data are in a fixed time relationship with the transmitter pulse signal. In the course of the transmission of a data signal through a transmission channel K.sub.1, this correct, fixed time reference of the data signal to the transmission pulse signal is lost. The reasons for this are the limited transmission band width of the transmission channels K.sub.1, interference signals, time variable decision thresholds of the inlet circuits of the repeaters R.sub.1, etc.
By means of a so-called NRZ (nonreturn to zero) signal this process is shown in FIG. 2c, wherein the amplitude regeneration has already taken place. Also, the phase shift caused by the running time of the data signal in the transmission channel K.sub.1 between the data at the inlet and the outlet of a transmission channel K.sub.1, is neglected. Due to the loss of the correct time relationship between the transmitter pulse signal and the data signal, the shaded area shown in FIG. 2c with an undefined phase, is obtained. This phase trembling, also referred to as jitter, changes the spectral properties of the data signal and must be minimized in order to allow pulse derivation free to errors in the receiver and thus a correct, error-free interpretation of the data signal in the receiver circuit. The pulse regeneration in the repeater R.sub.1 has the function to retransmit the data signal without jitter.
In the following, the properties and parameters of the CSMA/CD transmission process according to the IEEE standard 802.3 are described, which are valid for the repeaters R.sub.1 and which the repeaters R.sub.1 are to satisfy.
One of the properties of the CSMA/CD access process is that the transmitted data are divided into individual packets. the packets are made up of a preamble, segment and useful data.
The preamble includes a regular data pattern without information, which allows the receivers, i.e., the participants or computers T.sub.1 and the repeaters, to synchronize them on a data packet received. The minimum length of the preamble is specified and according to the IEEE standard 802.3 is 56 bits.
The control information and useful data part contains control information and the useful data themselves. The minimum and maximum lengths of said control and useful data parts are also specified and amount in this process to 512 bits as the minimum length and 12 144 bits as the maximum length.
Furthermore, the minimum time spacing in which the data packets may be transmitted is also specified. This spacing, which is also designated as the packet spacing or inter frame gap (IFG), may be 96 us. The minimum time spacing makes it possible for the participants and the computers T.sub.1 to prepare themselves following the completion of a data packet for the reception of the next one.
The maximum running time of a data packet between the two farthest removed participants or computers T.sub.1 is also specified in the network. In the case of the network discussed here, this maximum running time amounts to 25.6 us. At a given propagation velocity of the signals in the transmission channels K.sub.1 the maximum spatial extent of the network with a known running time lag and known number of repeaters is specified. In the case of the CSMA/CD access process according to the aforementioned standard, this maximum spatial extension amounts to 5 km.
A further parameter of said access process according to the standard cited is the bit rate which amounts to 1.times.10.sup.7 bits/s and is allowed a maximum deviation of .+-.0.01%. The so-called Manchester code is used for coding, which in addition to the useful data also contains supplemental pulse information, thereby making possible secure pulse derivation by the computers T.sub.1 and the repeaters, independently of the data content.
From the aforementioned properties, i.e., the structure of the data packet, the minimum time spacing between data packets and the maximum running time of a data packet in the network, the following requirements are derived relative to the pulse regeneration of a repeater R.sub.1 in a CSMA/CD network according to the IEEE Standard 802.3.
1. If the length of the preamble during the passage of a data packet through a repeater were shortened, it would indicate that when several successive repeaters are used the preamble would be successively shortened further, until finally the synchronization of a participants or another repeater on the data packet would no longer be possible. Therefore, there exists the requirement that the length of the preamble in the course of the passage of a data packet through a repeater not be shortened, while a possible extension of the preamble is permissible.
2. If the time spacing between two successive data packets were shortened below a certain minimum value by the use of repeaters, this would signify that the packet spacing in the cascading of several repeaters would be progressively reduced, which in turn would limit the number of repeaters to be inserted in succession. There are no standards at the present time specifying minimum spacing at the receiver. However, there are draft standards specifying a minimum spacing of about 5 us. In the use of repeaters in the networks it must therefore be required that the time spacing between two successive data packets through a repeater be not shortened, or shortened by a certain amount only.
3. A further requirement relative to a repeater is that the start-up lag, also referred to as a start-up-delay should be as small as possible, as explained in more detail hereinbelow. The start up delay is the time elapsing between the receipt of the first preamble bit of a data packet and the retransmission of the data packet amplitude and/or pulse regenerated. The start up delay increases the running time of a data packet within the network, thereby reducing its maximum spatial extent; or in other words, a given spatial extent of a network limits the number of cascadable repeaters.
FIG. 3 shows the fundatmental structure of a conventional circuit layout for pulse regeneration in a repeater.
The receiving data signal is applied to the inlet 31 of the pulse regeneration circuit; it arrives at a pulse derivation and decoding stage 32. The pulse derivation and decoding stage 32 derives a receiving pulse signal from the receiving data signal, which in case of a network is Manchester coded according to the IEEE Standard 802.3 and converts it into the NRZ format. The NRZ data signal arrives through a line 33 at the inlet of a buffer memory 34. The receiving pulse signal passes through a line 35 as a read-in pulse signal to the read-in pulse signal inlet of the buffer memory 34.
The pulse signal derivation from the receiving data signal is carried out in the pulse derivation and decoding stage 32 usually by means of, a phase control circuit, also referred to as a Phase Lock Loop (PLL), whereby a local oscillator is synchronized with the preamble of the receiving data signal. Following the completion of the synchronization process a so-called RX carrier signal is generated, which arrives through the line 36 at a control circuit 37.
Through a line 38 a readout release signal arrives at a coder 39, which provides for the buffer memory 34 a transmission pulse signal as the readout pulse signal through the line 40, so that correspondingly the NRZ coded data is read out through the line 41 from the buffer memory 34 and converted in the coder 39 into Manchester coded data, so that at the outlet 42 a transmission data signal is present. As the data of the transmission data signal are in a fixed time relationship with the readout and transmission pulse signal, the transmission data signal is free to phase jitters.
The control circuit 37 transmits over the line 43 a read-in release signal to the buffer memory 34. Over a line 44, the control circuit 37 receives a so-called DOR signal, which indicates when the buffer memory 34 is completely read out. A transmission pulse generator 45 produces the transmission pulse signal for both the control circuit 37 and the coder 39.
The buffer memory 34 is preferably realized in keeping with the FIFO (first in, first out) principle and allows an independent, synchronous in- and out reading of data. The read-in of the receiving data signals appearing in the line 33 into the buffer 34 takes place synchronously with the receiving pulse signal standing at the line 35. The data are read out from the buffer memory 34 synchronously with the readout pulse signal in the line 40, which is identical with the local transmission pulse signal. The transmission pulse signal is asynchronous relative to the receiving pulse signal.
The number of bits to be stored intermediately in the buffer memory 34 depends on the frequency difference between the transmission and receiving pulse signal and the maximum length of the data packet. This condition is numberically visualized by the specifications of IEEE Standard 802.3.
According to the CSMA/CD process in keeping with said standard, the bit rate amounts to 1.times.10.sup.7 bits/s with a maximum deviation of .+-.0.01%, i.e. .+-.1.times.10.sup.3 bits/s. Without the preamble, the maximum packet length is 12 144 bit/s.
With a minimum bit rate, the packet duration has a minimum length of L2+1.214279 ms.
The difference between L1 and L2 thus amounts to 242 ns. As at a bit rate of 1.times.10.sup.7 bit/s the bit time is 100 ns, this time difference of 242 ns corresponds approximately to 2.5 bit times. This signifies that at least 3 bits must be stored intermediately. If read-in takes place at the minimum permissible bit rate and the readout at the maximum permissible bit rate, i.e. the readout is faster than the read-in, the buffer memory must contain prior to the readout at least 3 bits, in order to insure that upon each readout pulse at least one bit is present in the buffer memory.
If, on the other hand, the read in is at the maximum bit rate and readout at the minimum bit rate, three additional bits must be stored intermediately. The minimum buffer memory capacity, also referred to as the minimum depth of the buffer memory, must therefore amount to at least 6 bits.
The figures determined here represent theoretical minimum values, wherein it is assumed in particular that the bit rates are within the tolerance limits specified. In the case of commercially inserted repeaters usually more than 3 bits are stored intermediately in order to reduce the sensitivity to fluctuations of bit rates, thereby increasing operating security.
The number of intermediately stored bits essentially determines the static running time of a pulse generating circuit. The static running time is the time between reception and retransmission of the same bit by a repeater. The concept of the static running time should not be confused with the aforementioned start up delay, which is defined as the time between the reception of the first preamble bit of a data packet and the retransmission of the first preamble bit of the amplitude and pulse regenerated data packet.
If n bits are stored intermediately and the transmission and receiving pulses are in agreement, the static running time is equal to or larger than n bit times.
The control circuit 37 controls the buffer memory 34 and the coder 39 over the line 43 and 38, respectively.
If the aforementioned synchronizing process in the pulse derivation and decoding stage 32 is completed and the receiving data signal and the receiving pulse signal are available at the outlet of said stage 32, this fact is communicated over the line 36 by means of the R.sub.x carrier signal to the control circuit 37, which depending on it releases the read in into the buffer memeory over the line 43. If an adequate number of data are stored in the buffer so that in the case of maximally different read in and readout velocities always at least one bit is available for the readout process, the readout is released by the coder 39.
At the end of a data packet, which is indicated to the control circuit 37 by the R.sub.x data signal, the control circuit 37 blocks the reading in of additional bits into the buffer memory 34. If the buffer 34 is then completely read out, which is indicated to the control circuit 37 over the line 44 by the DOR signal, the control circuit 37 blocks the readout of the buffer 34 by the coder 39 over the line 38. The transmission of a data packet is thereby completed.
The functional group of the pulse derivation and decoding stage 32 and the coder 39 may be an Advanced Micro Devices Company (AMD) AM7992B and described in the corresponding data sheets of the company. The control unit for such a repeater is marketed by the AT&T Microelectronics Co. in the form of the electronic module T7200 Multi-Port Repeater Unit Controller and is described in the corresponding data sheet. With this module at least 7 bits are stored intermediately. An example for a buffer memory 34 is the electronic module 74HCT40105 of the Valvo Co., which again is described in a data sheet of the company.
The transmission pulse generator 45 and its oscillator must satisfy relative to its frequency accuracy the requirements of the standard selected.
With respect to FIG. 4, in the following the variations of the data packet during its passing through the conventional pulse signal regeneration circuit shown in FIG. 3 is explained.
FIG. 4a shows the spatial distribution of a data packet at a time t=to, wherein it is assumed hypothetically that said data packet has passed through the repeater unaffected. In FIG. 4b the data packet altered by the repeater is shown.
The data packet always includes control information and a useful data part 48a and 48b, and the preamble 49a and 49b. The startup delay 50 is the sum to the time loss generated by the synchronizing process in the pulse derivation and decoding stage 32, and the static running time 51. The time loss caused by the synchronizing process amounts for example in the case of the electronic module AM7992B to at least four bit times. The combination of this module AM7992B with a repeater of 7 bits corresponding to the aforementioned module T7200 of AT&T would result in a startup time delay of 50 of about 1.1 us. In a computer network according to IEEE 802.3, in which the maximum running time of a data packet between the two participants T.sub.1 farthest removed in the network amounts of 25.6 us, in case of a successive insertion of 25.6/1.1=23 repeaters the permissible extent of the network would therefore be reduced to 0, wherein the additional running time delays caused by individual circuit components (part of the pulse derivation and decoding stage 32), buffer memory 34 and coder 39, are neglected.
As explained above, preamble bit losses 52 occur. Due to the synchronizing process in the pulse signal derivation, some bits of the preamble are consumed, for example, at least 4 bits in the case of the AM7992B module. With a preamble length of 56 bits the data bits would have no preamble after passing through 14 repeaters.
As the startup time delay 50 is larger than the static running time 51, the time spacing of two successive data packets increases with each repeater.
The discussion presented in the foregoing clearly indicates that with the circuit shown in FIG. 3 the aforedescribed requirement relative to a repeater that the length of the preamble must not be reduced and that the startup time delay should be as short as possible, cannot be satisfied. The use of the circuit layout shown in FIG. 3 is possible in a network according to IEEE 802.3 to a very limited extent only.
FIG. 5 displays schematically a known extended pulse regeneration circuit. The circuit components in FIG. 5, which correspond to those in FIG. 3, are provided with the same reference symbols and are not explained again.
The circuit layout according to FIG. 5 differs from that of FIG. 3 in that additionally a carrier recognition stage 55 and a stage 56 to produce a synthetic preamble, referred to hereafter as a preamble generator, are provided. The inlet of the carrier recognition stage 55 is connected by a line 60 to the inlet 31 of the pulse regeneration circuit, so that the carrier recognition stage 55 is able to detect the onset of a preamble of an incoming data packet. This information is conducted to the control circuit 37 over the data line 57 with the signal "data present". By a line 58 the control circuit 57 is connected to a preamble generator 56, the outlet signal arrives over the line 59 at the coder 39. The preamble generator 56 further receives the readout pulse signal on the line 40 which also constitutes the transmission pulse signal.
The carrier recognition stage 55 has a configuration such that the time delay between the onset of the preamble appearing at its inlet and the report to the control circuit 37 is very small, preferably shorter than one bit time. The control circuit 37 there is informed even prior to the completion of the synchronizing process in the pulse derivation and decoding stage 32 of the arrival of a data packet at the pulse regeneration circuit.
The structure of the preamble at the beginning of a data packet is unambiguously determined. It is therefore possible to transmit a synthetic preamble in place of the preamble received. The preamble generator 56 performs this task and produces a synthetic preamble.
When the control circuit 37 is informed by the carrier recognition stage 55 of the reception of data packet, it activates following a selective waiting period the preamble generator 56 over the line 58 and the coder 39 over the line 38. If the waiting period is chosen to be small or practically zero, the synthetic preamble has already been sent out prior to the completion of the synchronization for the pulse derivation and before the buffer memeory 34 has stored an adequate number of bits. This signifies that the startup time delay may be very small.
If since the onset of the appearance of an incoming data packet is sufficiently long period of time has passed to fill upon the memory 34, the preamble generator 56 is deactivated and the memory 34 released. Consequently, in place of the synthetic preamble from this point in time on the preamble received is transmitted.
The further progress to the end of the data packet now corresponds to the pulse generation circuit shown in FIG. 3 and therefore is not explained further.
FIG. 6, shows the schematic spatial configuration of data packets. The changes applied to a data packet during its passage through a pulse generation circuit according to FIG. 5 are explained below.
FIG. 6a shows the spatial distribution of the unaffected data packet at a time t=to with the hypothetical assumption that the data packet has passed through the repeater without alterations. In FIG. 6b, the data packet altered by the pulse regeneration circuit shown in FIG. 5 is reproduced. The parts of the data packet, preambles and durations, to the extent that they correspond to those in FIG. 4, are provided with the same symbols and are not discussed further.
From a comparison of the unaffected data packet and the one altered by the pulse generation circuit, the following may be derived:
As the carrier recognition stage 55 immediately detects the onset of an incoming data packet, a synthetic preamble part 61 may be transmitted, which is followed by the transmission of the preamble part 62 received, when the synchronizing process in the pulse generation and decoding stage 32 is completed.
It follows that compared to the data packet altered by the circuit in FIG. 3, according to the FIG. 4b the startup time delay, i.e., the period of time between the reception of the first preamble bit and the first re-transmission bit of a data packet is small. Another advantage of the pulse regeneration circuit according to FIG. 5 relative to that of FIG. 3 is that the preamble is not shortened. A further consequence is that the packet spacing or inter frame gap is reduced by the difference between the startup time delay and the static running time.